1. Field of the Invention
The present invention relates to a parallel test mode for memory device, and more particularly to a parallel test circuit for memory device capable of improving test efficiency by which a single main amplifier compares and amplifies two-bit data.
2. Discussion of the Background
FIG. 1 is a simplified schematic diagram of a four-bit parallel test circuit for DRAM according to a conventional art.
As shown therein, the conventional four-bit parallel test circuit includes: an input/output pad 100 for receiving four-bit identical data in a test mode and for outputting resultant data after the test; an input circuit unit 110 for receiving the data from the input/output pad 100 in accordance with a write enable signal; a write driving unit 120 for transmitting the four-bit data from the input circuit unit 110 in accordance with the write enable signal via 4 IO line couples 101T/B, 102T/B, 103T/B, 104T/B, for thus being written in each memory; a memory mat unit 130 provided with 4 memory mats MAT1, MAT2, MAT3, MAT4, each having a memory cell wherein the four-bit data are respectively written and stored and an X, Y address decoder for accessing the memory cell; a main amp unit 140 provided with 4 main amplifiers M/A1, M/A2, M/A3, M/A4 for respectively amplifying a feeble voltage difference between two signals supplied through coupled line T and line B of the IO line couples 101T/B, 102T/B, 103T/B, 104T/B, respectively connected to the main amplifiers M/A1, M/A2, M/A3, M/A4 in accordance with a read enable signal, and outputting the amplified voltage difference as an one-bit logic value; a data reducing unit 150 for reducing four-bit data outputted from the main amplifiers M/A1, M/A2, M/A3, M/A4, respectively, to a one-bit data signal in accordance with the read enable signal; and an output circuit unit 160 for outputting the data from the data reducing unit 150 to the input/output pad 100.
Now, a four-bit parallel test process for DRAM according to the conventional art will be described.
First, when four-bit identical data are inputted through the input/output pad 100 for the test, the input circuit unit 110 and the write driving unit 120 are driven in accordance with the write enable signal, and the four-bit data are supplied to the 4 IO line couples 101T/B, 102T/B, 103T/B, 104T/B, respectively, and written in the memory mats MAT1, MAT2, MAT3, MAT4 of the memory mat unit 130.
Here, since the read enable signal is not enabled, other block units may not be operated.
When the data write operation in the memory mat unit 130 is completed, the read enable signal is enabled and accordingly the main amp unit 140, data reducing unit 150, and output circuit unit 160 are operated.
An one-bit data signal supplied through the coupled line T and the line B connected to each of the memory mats MAT1, MAT2, MAT3, MAT4 of the memory mat unit 130 becomes an input signal of each of the main amplifiers M/A1, M/A2, M/A3, M/A4 of the main amp unit 140.
Here, each coupled lines T and B of the four IO line couples, which are inputted to the main amp unit 140, have a slight voltage difference. Each of the main amplifiers M/A1, M/A2, M/A3, M/A4 of the main amp unit 140 amplifies the voltage difference and determines an output signal MOCi (I=1,2,3,4) as a logic `1` or `0` with respect to each input signal in accordance with a value of the amplified voltage difference.
Next, the data reducing unit 150 compares the four-bit data signals MOCi (I=1, 2, 3, 4) outputted from the main amplifiers M/A1, M/A2, M/A3, M/A4 of the main amp unit 140, and thus outputs `1` when the four-bit data signals are identically `1` or `0` and outputs `0` when at least an one-bit data signal has a different logic value.
The one-bit data signal reduced by the data reducing unit 150 is transmitted to the input/output pad 100 through the output circuit unit 160.
Lastly, when the data transmitted to the input/output pad 100 is `1`, it is considered that the write and read operation for the four-bit data are normally carried out, while the data is `0`, at least an one-bit data signal is erroneously operated.
According to the conventional parallel test method, since the data signals transmitted from the memory mats to the lines IOi T/B are the signals having the slight voltage difference, each main amplifier should amplify the data signals to compare a data logic of each parallel bit data.
Thus, since each main amplifier takes charge of an one-bit data signal, only an n bit parallel test is possible in DRAM provided with an n number of main amplifiers.